Jianwei Jia
Affiliation: Laboratory for Emerging Devices and Circuits , ECE, Gatech
Jianwei Jia is currently a third-year Ph.D. student at the Georgia Institute of Technology, supervised by Prof. Shimeng Yu. He received the B.S. degree in Microelectronics from Nankai University in 2021 and the M.S.E. degree in VLSI from the University of Michigan - Ann Arbor, in 2023.
His research focuses on leveraging emerging non-volatile devices, such as ferroelectric field-effect transistors (FeFETs), ferroelectric capacitors (FeCAPs), and resistive RAM (RRAM), to enhance the performance and expand the functionality of conventional CMOS circuits. His work spans both analog and digital design domains, including computing-in-memory (CIM), ternary content-addressable memory (TCAM), and reconfigurable analog circuit architectures.
He has led more than five chip tapeouts and has extensive experience with both open-source and commercial EDA tools. His design work spans multiple technology nodes and PDKs, including SkyWater130, Ti LBC7, GF 28SLPe (FEOL FeFET platform), GF 22FDX (BEOL FeCAP platform), TSMC N16, and TSMC N7. He has published in leading conferences such as ASPDAC, ISCAS, and MWSCAS, as well as journals including IEEE JXCDC and IEEE EDL. He is currently a Graduate Student Member of the IEEE and serves as a reviewer for several IEEE journals, including TCAS-II, EDL and IEEE Trans. Comput.
news
| Mar 30, 2026 | Our new publication “Non-Volatile Digital Compute-in-Memory Macro with Ferroelectric FET-based Voltage Divider Weight Cells Featuring Power-Gating” has been accepted by OJ-SSCS now!  In this work, we present a non-volatile digital CIM (nvDCIM) macro in GlobalFoundries 28-nm, utilizing a novel dual FeFET voltage divider bitcell for lossless MAC operations with non-volatile weight storage. Power-gating enables 77.7% total power reduction at 1% activity factor with no weight-reload penalty, while active compute achieves 106.6 TOPS/W — competitive with conventional SRAM-based DCIM. The macro matches software baseline accuracy (89.66%) on CIFAR-10 with VGG-8. |
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| Dec 03, 2025 | Our new publication “A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC” has published on SSCL now! In this work, we present a 4-kb FeFET-CIM macro fabricated in GlobalFoundries 28-nm HKMG process, featuring a 64×64 crossbar array with on-chip 4-bit Flash ADCs. We propose an ISPP scheme to reduce current variation and achieve 346.6 TOPS/W energy efficiency — a 9.5× improvement over our prior 40-nm RRAM-CIM macro. The macro reaches 89.1% inference accuracy on CIFAR-10 (VGG-8), close to the 89.7% software baseline. |
| Sep 07, 2025 | Our new publication “Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems” has published on arXiv now! |
