Jianwei Jia
Affiliation: Laboratory for Emerging Devices and Circuits , ECE, Gatech
I am currently a third-year Ph.D. student at the Georgia Institute of Technology, supervised by Prof. Shimeng Yu. I received the B.S. degree in Microelectronics from Nankai University in 2021 and the M.S.E. degree in VLSI from the University of Michigan - Ann Arbor, in 2023.
My research advances AI accelerator chips through cross-domain co-design of analog, digital, and memory circuits, including computing-in-memory (CIM), in-memory search (CAM/TCAM), and reconfigurable analog architectures. My work spans novel memory cell design (e.g., gain-cell eDRAM) and the use of emerging non-volatile devices (FeFET, FeCAP, RRAM, MRAM) to enhance conventional CMOS circuits.
I have led 5+ chip tapeouts across technology nodes from SkyWater 130nm to TSMC N7, including ferroelectric platforms (GF 28SLPe, GF 22FDX), with extensive experience in open-source and commercial EDA flows. My work has been published at ESSERC, ASPDAC, and ISCAS, and in journals including IEEE TVLSI, SSCL, and EDL. I serve as a reviewer for TCAS-II, EDL, and IEEE Trans. Comput.
news
| May 28, 2026 | Our paper “aF-Resolution On-Chip Characterization of Sub-fF Non-Volatile Capacitance in Nanoscale FeFET” has been accepted for oral presentation at 2026 IEEE ESSERC, to be held in Palma de Mallorca, Spain, September 7–10, 2026. This work directly measures the on/off ratio of 1um x 1um ~ 200 nm × 200 nm nvCAP devices on-chip, exploring the scalability of data intensive nvCAP-based edge AI accelerators. |
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| May 11, 2026 | I have started a 6-month internship at TSMC North America (San Jose) as a Circuit Research Intern! |
| Mar 30, 2026 | Our new publication “Non-Volatile Digital Compute-in-Memory Macro with Ferroelectric FET-based Voltage Divider Weight Cells Featuring Power-Gating” has been accepted by OJ-SSCS now! In this work, we present a non-volatile digital CIM (nvDCIM) macro in GlobalFoundries 28-nm, utilizing a novel dual FeFET voltage divider bitcell for lossless MAC operations with non-volatile weight storage. Power-gating enables 77.7% total power reduction at 1% activity factor with no weight-reload penalty, while active compute achieves 106.6 TOPS/W — competitive with conventional SRAM-based DCIM. The macro matches software baseline accuracy (89.66%) on CIFAR-10 with VGG-8. |
| Dec 03, 2025 | Our new publication “A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC” has published on SSCL now! In this work, we present a 4-kb FeFET-CIM macro fabricated in GlobalFoundries 28-nm HKMG process, featuring a 64×64 crossbar array with on-chip 4-bit Flash ADCs. We propose an ISPP scheme to reduce current variation and achieve 346.6 TOPS/W energy efficiency — a 9.5× improvement over our prior 40-nm RRAM-CIM macro. The macro reaches 89.1% inference accuracy on CIFAR-10 (VGG-8), close to the 89.7% software baseline. |
| Sep 07, 2025 | Our new publication “Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems” has published on arXiv now! |
selected publications
- ESSERCaF-Resolution On-Chip Characterization of Sub-fF Non-Volatile Capacitance in Nanoscale FeFETIn 2026 IEEE European Solid-State Electronics Research Conference (ESSERC), Sep 2026Accepted
