Announcement_sscl

Our new publication “A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC” has published on SSCL now! In this work, we present a 4-kb FeFET-CIM macro fabricated in GlobalFoundries 28-nm HKMG process, featuring a 64×64 crossbar array with on-chip 4-bit Flash ADCs. We propose an ISPP scheme to reduce current variation and achieve 346.6 TOPS/W energy efficiency — a 9.5× improvement over our prior 40-nm RRAM-CIM macro. The macro reaches 89.1% inference accuracy on CIFAR-10 (VGG-8), close to the 89.7% software baseline.